DFT 2014 - Call for Papers

CALL FOR PAPERS

Scope -- Submissions -- Key Dates -- Additional Information -- Committees

Scope

DFT is an annual Symposium providing an open forum for presentations in the field of defect and fault tolerance in VLSI and nanotechnology systems inclusive of emerging technologies. One of the unique features of this symposium is to combine new academic research with state-of-the-art industrial data, necessary ingredients for significant advances in this field. All aspects of design, manufacturing, test, reliability, and availability that are affected by defects during manufacturing and by faults during system operation are of interest.

The topics include (but are not limited to) the following ones:

Yield Analysis and Modeling Defect/Fault analysis and models; statistical yield modeling; critical area and metrics.
Testing Techniques Built-in self-test; delay fault modeling and diagnosis; testing for analog and mixed circuits; signal and clock integrity.
Error Detection, Correction, and Recovery Self-testing and self-checking solutions; error control coding; fault masking and avoidance; recovery schemes, space/time redundancy; hw/sw techniques.
Dependability Analysis and Validation Fault injection techniques and environments; dependability characterization.
Defect and Fault Tolerance Reliable circuit/system synthesis; radiation hardened/ tolerant processes & design; design space exploration for dependable systems, transient/soft faults and errors.
Design For Testability in IC Design FPGA, SoC, NoC, ASIC, microprocessors.
Repair, Restructuring and Reconfiguration Repairable logic; reconfigurable circuit design; DFT for on-line operation; self-healing.
Totally Fail-Safe Design for Critical Applications Methodologies and case study applications to automotive, railway, avionics, industrial control, biomedicine, space and smart power networks.
Emerging Technologies Techniques for CNTs, QCA, DNA, RTDs, SETs, molecular devices and self-assembly.
Hardware security Fault attacks, fault tolerance-based countermeasures, Scan-based attacks and countermeasures, hardware trojans, security vs reliability trade-offs, interaction between VLSI test, trust, and
reliability.

Submissions

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Paper Submission: Prospective authors are invited to submit original and unpublished contributions (6 pages - with the opportunity to purchase 2 additional ones - in the IEEE conference template, 2-columns style, available on conference web site), to be submitted as PDF file, electronically. Please refer to the symposium web page for updated information:

http://www.dfts.org

We are also interested in panel sessions that involve industrial experiences: please send an email to the Program co-Chairs with a brief description (1 page max) of the proposed panel.

Paper Publication and Author Registration: Only original, unpublished work will be accepted, for regular or poster presentation at the symposium. Proceedings will be published by the IEEE Computer Society and will appear in the Digital Library.

Every accepted paper MUST have at least one full paid registration by the time the camera-ready paper is submitted for inclusion in the proceedings, and the author is expected to attend the Symposium and present the paper.

Best Student Paper Award: All papers with a student as both primary author and presenter will be taken into consideration for the 2014 Best Student Paper Award.

Key Dates

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Submission deadline: May 9th, 2014
Notification of acceptance: June 20th, 2014
Final copy deadline: July 25th, 2014

Additional Information

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For general information, contact the General co-Chairs. For paper submission information, contact the
Program co-Chairs. For all updated information, visit our web page.

Committees

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General co-Chairs
Said Hamdioui
Delft University of Technology, NL
E-mail: s.hamdioui@tudelft.nl

Marco Ottavi
Univ. of Rome “Tor Vergata”, IT
E-mail: ottavi@ing.uniroma2.it

Program co-Chairs
Sandip Kundu
UMass Amherst, USA
E-mail: kundu@ecs.umass.edu

Salvatore Pontarelli
CNIT, Italy
E-mail: pontarelli@ing.uniroma2.it

Industrial liasons Chair
Prashant Joshi
Intel, USA

Publication Chair
Qiaoyan Yu
Univ. of New Hampshire, USA

Publicity Chair
Antonio Miele
Politecnico di Milano, ITALY

Technical Program Committee
P. Ampadu, University of Rochester
L. Anghel, TIMA
C. Bolchini, Politecnico di Milano
G. Chapman, Simon Fraser University
L. Chen, University of Saskatchewan
Y. Choi, Hongik University
R. Cideciyan, IBM
A. Cristian, BSC
A. Daniel, Intel
S. Das, ARM,
L. Dilillo, LIRMM
B. Eklow, CISCO
O. Ergin, TOBB
A. Evans, IROC
M. Fukushi, Yamaguchi University
D. Gizopoulos, University of Athens
J. Han, University of Alberta
C. Huang, Nat’l Tsing Hua University
N. Jha, Princeton
W. Jone, University of Cincinnati
N. Karimi, NY Poly
R. Karri, NY Poly
Y. Kim, Northeastern University
I. Koren, UMASS Amherst
L. Lastras IBM,
R. Leveugle, TIMA
X. Li, Chinese Academy of Science
H. Li, Chinese Academy of Science
F. Lombardi, Northeastern University
C. Metra, University of Bologna
M. Michael, University of Cyprus
A. Miele, Politecnico di Milano
M. Mozaffari Kermani Rochester IT
K. Namba, Chiba University
N. Nicolici, McMaster University
N. Park, Oklahoma State University
A. Paschalis, University of Athens
Z. Peng, Linkoping University
W. Pleskacz, Warsaw U.T.
I. Pomeranz, Purdue University
S. Reddy, University of Iowa
P. Reviriego, University of Nebrjia
D. Rossi, University of Bologna
F. Salice, Politecnico di Milano
D. Sciuto, Politecnico di Milano
O. Sinanoglu, N.Y.U. Abu Dhabi
V. Sridharan, AMD
M. Tehranipoor, U. of Connecticut
J. Teixeira, Técnica de Lisboa
C. Thibeault, Ecole de Tech.
N. Touba, Univ. Texas at Austin
S. Tragoudas, S. Illinois U. Carbondale
M. Violante, Politecnico di Torino
L. Wang, University of Connecticut
X. Wen, Kyushu Institute of Technology
D. Xiang, Tsinghua University
Q. Yu, University of New Hampshire

For more information, visit us on the web at: http://www.dfts.org

The IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT 2014) is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC).